This invention relates to semiconductor bus switches, and more particularly to bi-directional undershoot protection for a MOS bus switch.
Networkinig applications often employ bus switches. Bus switches using metal-oxide-semiconductor (MOS) technology have the advantage of low on resistance, reducing delay through the switch. The source and drain nodes of the bus-switch transistor connect to the busses while the gate is controlled by a bus-conecting enable signal. See for example xe2x80x9cParallel Micro-Relay Bus Switch for Computer Network Communication with Reduced Crosstalk and Low On-Resistance using Charge Pumpsxe2x80x9d, U.S. Pat. No. 5,808,502, and xe2x80x9cBus Switch Having Both P- and N-Channnel Transistors for Constant Impedance Using Isolation Circuit for Live-Insertion when Powered Downxe2x80x9d U.S. Ser. No. 09/004,929, now U.S. Pat. No. 6,034,553.
More complex networks are emerging. For example, the bus switch may connect two processor buses. Each processor bus can operate independently of the other. Hot-plugging or hot-swapping of cards with the processor bus can also occur. When the bus switch is in the isolation mode, full isolation must occur, regardless of which bus is active.
FIG. 1 shows a typical application of a bus switch. First local bus signals 18 (bus A) is connected to CPU_A 10, memory_A 14, and Application-Specific Integrated Circuit (ASIC_A) 12. Second local bus signals 19 (bus B) is a second local bus that has CPU_B 11, memory_B 15, and Application-Specific Integrated Circuit (ASIC_B) 13. Second local bus signals 19 is a hot-plugable bus. Switch network 16 connects address, data, and control lines from bus signals 18 to bus signals 19 using MOS transistors. One transistor is used for each bus signal.
When a device is plugged into bus signals 19, it may be desired to isolate bus signals 19 from local bus signals 18. Noise caused by the plugging operation can then be isolated to bus signals 19, allowing local bus signals 18 to operate unhindered. Switch network 16 can isolate bus signals 19 from local bus signals 18 by applying a low voltage to n-channel transistors in switch network 16. When switch network 16 isolates, Bus_A can operate independently of Bus_B.
Either Bus_A or Bus_B may be hot-plugged into the other bus. This allows for repair of systems without any downtime. Isolation by switch network 16 must therefore be fully bi-directional since it is not known which bus will be replaced until a failure occurs.
Undershoot Problem
When an n-channel transistor is used as the bus switch, the bus switch is disabled by driving a ground voltage to the gate of the n-channel bus-switch transistor. The output bus signal should be isolated from voltage changes at the input bus signal. The quality of the signal waveforms on local bus signal 18 is not always well controlled. Sometime large voltage spikes below ground (undershoots) occur, especially on the high-to-low transitions from high-current drivers on local bus signal 18. The same could occur on bus signals 19.
When the bus-switch input from bus signal 18 goes below ground, a positive gate-to-source voltage develops on bus-switch transistor since its gate is at ground. A conducting channel forms below the gate. When the undershoot is greater than a volt, this gate-to-source voltage exceeds the n-channel threshold voltage, turning on the n-channel bus switch transistor. Some current is conducted through the channel of the bus-switch transistor even though its gate may be kept at ground. The result is that the voltage is disturbed on the drain of the bus-switch transistor, and the output to bus 19.
When the source of the n-channel bus-switch transistor goes negative during the undershoot, the base-emitter junction of the parasitic lateral NPN transistor is forward biased, coupling more current to the output through the p-type substrate.
The result of the undershoot is that the output connects to the input for a short period of time, the duration of the undershoot. The voltage on the drain of the bus-switch transistor can quickly fall from the power supply (Vcc) to ground and even below ground should the undershoot last for more than a few nanoseconds. The undershoots on the input bus coupled to the output, producing severe voltage disturbances on the isolated bus.
The co-inventor has solved an undershoot-isolation problem in an earlier patent, U.S. Pat. No. 6,052,019 for xe2x80x9cUndershoot-Isolating MOS Bus Switchxe2x80x9d. However, this patent shows a circuit that is effective when the undershoot always occurs on only one side of the bus switch. An improved circuit is desired that can isolate undershoots that would occur on either side of the bus switch. A fully bidirectional undershoot-isolating bus switch is desired.
What is desired is a fully bidirectional bus switch using CMOS technology. Protection from undershoot on the input or output side is desired when the bus switch is isolating its output from its input. An active undershoot-protection circuit using CMOS transistors is desired. It is desired to maintain the low on-resistance and low capacitance of the bus switch. A more fully-isolating and bi-directional bus switch is desirable.
A bi-directional-undershoot-protected bus switch has a first bus input connected to a first bus and a second bus input connected to a second bus. A bus switch transistor has a source connected to the first bus input and a drain connected to the second bus input and a gate connected to a gate node.
A first connecting transistor has a source connected to the first bus input and a drain connected to a first intermediate node. It connects the first bus input to the first intermediate node in response to a first activating signal applied to a first activating node connected to a gate of the first connecting transistor. A first fixed-gate transistor has a source connected to the first immediate node and a drain connected to the gate node and a gate connected to a fixed voltage. It connects the first intermediate node to the gate node during an undershoot on the first bus input.
A second connecting transistor has a source connected to the second bus input and a drain connected to a second intermediate node. It connects the second bus input to the second intermediate node in response to a second activating signal applied to a second activating node connected to a gate of the second connecting transistor. A second fixed-gate transistor has a source connected to the second immediate node and a drain connected to the gate node and a gate connected to a fixed voltage. It connects the second intermediate node to the gate node during an undershoot on the second bus input.
A first activating transistor has a drain connected to the first activating node. It generates the first activating signal to protect from the undershoot on the first bus input. A second activating transistor has a drain connected to the second activating node. It generates the second activating signal to protect from the undershoot on the second bus input.
An enable input is for indicating an isolation mode when the bus switch transistor isolates the first bus input from the second bus input. A pullup transistor has a gate responsive to the enable input. It drives the gate node high when the isolation mode is not active. A discharge transistor drives the gate node low when the isolation mode begins. Thus the bus switch transistor is protected from undershoots on the first and second bus inputs.
In further aspects of the invention the first and second fixed-gate transistors are n-channel transistors with gates connected to ground. The fixed voltage is ground. Thus grounded-gate transistors couple the undershoot to the gate node.
In further aspects the first and second connecting transistors are n-channel transistors. The first activating transistor is a p-channel transistor having a drain connected to the first activating node and a source connected to a power supply and a gate connected to a first trigger node. The second activating transistor is a p-channel transistor having a drain connected to the second activating node and a source connected to the power supply and a gate connected to a second trigger node. Thus p-channel transistors generate the first and second activating signals.
In further aspects of the invention a first sense-pulse circuit is coupled to the first bus input. It generates a pulse on the first trigger node in response to a low-going transition on the first bus input. A second sense-pulse circuit is coupled to the second bus input. It generates a pulse on the second trigger node in response to a low-going transition on the second bus input. Thus undershoot protection is triggered by low-going transitions on the first and second bus inputs.
In other aspects of the invention a direction input indicates when the first bus input is active and the second bus input is inactive. A first logic gate receives the direction input and the enable input; it drives the first trigger node. A second logic gate receives the direction input and the enable input. It drives the second trigger node. The direction input disables either the first activating transistor or the second activating transistor. Thus undershoot protection is enabled by logic gates selected by the direction input.